(Senior Principal) Silicon Evaluation Lead (SerDes)

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Job Title: (Senior Principal) Silicon Evaluation Lead (SERDES)Location: CorkReports to: Group DirectorJob Overview:The Silicon Evaluation Lead will manage the Silicon Evaluation team as part of a complete SERDES Product Team located at Cork, Ireland.Job Responsibilities:Manage the Silicon Evaluation team to validate High Speed SERDES products at data rates up to 112 Gbps on leading edge technology nodes (e.g. 3nm FinFET CMOS)Work with other technical domain leads and the program management team to deliver PHY products to the customer on scheduleAbility to hire and attract new team members to build and maintain a complete Silicon Evaluation teamWork with global teams and stakeholders across different time-zones (US, EU, India),Job Qualifications:BEng, MEng, PhD or equivalentCandidate’s background should include a minimum 10 years of silicon validation experience, preferably in the area of SERDES, DDR or high-speed interface designMust have at least 4 years' experience managing Silicon Evaluation Engineers as part a larger mixed signal product teamStrong understanding of lab equipment and measurement techniques for high speed interfaces (High speed scopes, probes, spectrum analyzers, BERTs)Must have a thorough understanding of eye diagrams, transmission lines, channel loss etc. along with associated jitter and signal equalization techniquesGood knowledge of the main board and package design approaches used in the industrySoftware proficiency for test scripting, data handling and reporting using scripting languages such as Python, TCL etc.Ability to run Verilog test benches and view waves to debug issuesExcellent interpersonal skills and ability to communicate effectively with both technical and nontechnical individualsExcellent problem-solving skills, and ability to work cooperatively in a team environmentCommunicate with global teams (US, India, China, EU) which work in different time-zonesLead Evaluation team to understand requirements, fashion tests and review resultsMentor Junior Engineers as requiredAdditional Skills/Preferences: Experience with chiplet substrate/package design methodologies and toolsFamiliarity with “pre-silicon” verification strategies and tool flowsInterest in publishing academic papers & presenting at conferences e.g. ISSCC, DesignConAdditional Information:Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace. Travel: >10%We’re doing work that matters. Help us solve what others can’t.